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Course Outline

The origins of RISC-V architecture, including the modular architecture definition comprising base architectures and extensions. Coverage of the RISC-V ISA, such as registers and the instruction set, along with features aligned with modern software concepts. An overview of RISC-V implementations is also provided.
RISC-V system architecture, focusing on exceptions and their management. Discussions on the CLIC interrupt controller and the ECLIC interrupt controller within the GD32VF103.

Practical Exercises:
1. Firmware development for the GD32VF103 using VSCode.
2. Implementing interrupts on the GD32VF103.

Requirements

Foundational knowledge of the C programming language.

 7 Hours

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